Bits for REG_SND{1,2,4}CNT (aka REG_SOUND1CNT_H, REG_SOUND2CNT_L, REG_SOUND4CNT_L, respectively) More...

Macros
#define	SSQR_DUTY1_8 0
	12.5% duty cycle (#----—)

#define	SSQR_DUTY1_4 0x0040
	25% duty cycle (##---—)

#define	SSQR_DUTY1_2 0x0080
	50% duty cycle (####-—)

#define	SSQR_DUTY3_4 0x00C0
	75% duty cycle (######–) Equivalent to 25%

#define	SSQR_INC 0
	Increasing volume.

#define	SSQR_DEC 0x0800
	Decreasing volume.

#define	SSQR_LEN_MASK 0x003F

#define	SSQR_LEN_SHIFT 0

#define	SSQR_LEN(n) ((n)<<SSQR_LEN_SHIFT)

#define	SSQR_DUTY_MASK 0x00C0

#define	SSQR_DUTY_SHIFT 6

#define	SSQR_DUTY(n) ((n)<<SSQR_DUTY_SHIFT)

#define	SSQR_TIME_MASK 0x0700

#define	SSQR_TIME_SHIFT 8

#define	SSQR_TIME(n) ((n)<<SSQR_TIME_SHIFT)

#define	SSQR_IVOL_MASK 0xF000

#define	SSQR_IVOL_SHIFT 12

#define	SSQR_IVOL(n) ((n)<<SSQR_IVOL_SHIFT)

#define	SSQR_ENV_BUILD(ivol, dir, time) ( ((ivol)<<12) \| ((dir)<<11) \| (((time)&7)<<8) )

#define	SSQR_BUILD(_ivol, dir, step, duty, len) ( SSQR_ENV_BUILD(ivol,dir,step) \| (((duty)&3)<<6) \| ((len)&63) )

Detailed Description

Bits for REG_SND{1,2,4}CNT (aka REG_SOUND1CNT_H, REG_SOUND2CNT_L, REG_SOUND4CNT_L, respectively)

Macros