#37131 - Gopher - Mon Mar 07, 2005 9:14 pm
Didn't find this answered in the forums or in the sound docs I've gone through, maybe I missed it though; If I'm just doing simple dma-driven playback on both channels at once, will I need to worry about timing them to not conflict? or are the channel timings already synched to avoid this in hardware?
By the time I get an answer I should be ready to test it, got some sound/tool work to do first
Thanks,
Gopher
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#37134 - tepples - Mon Mar 07, 2005 10:35 pm
I'm pretty sure that a write to SOUNDCNT_H (0x04000082) with both "Reset FIFO" bits set resets both FIFOs simultaneously.
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#37137 - Gopher - Mon Mar 07, 2005 11:35 pm
well, it's not synching playback of samples I'm concerned with, it's the potential dma conflict if both needed to do their dma writes at the same time.
I've already played with it tho and it seems not to be an issue. I was trying to anticipate problems, ended up worrying over a shadow this time, heh. (Isn't that the groundhog? It's a bad joke, but I wanted to head off anybody else who might have thought of making it :)
Gopher
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#37138 - tepples - Mon Mar 07, 2005 11:45 pm
| Gopher wrote: |
| it's not synching playback of samples I'm concerned with, it's the potential dma conflict if both needed to do their dma writes at the same time. |
DMA 0 always takes precedence over DMA 1, which takes precedence over DMA 2, which takes precedence over DMA 3. Typically, DMA 0 is used for hblank effects, DMA 1 for either a second hblank effect or stereo audio, DMA 2 for audio, and DMA 3 for memcpy(). But because of the FIFOs, even if DMA 0 takes all 224 or so usable cycles of hblank to execute, DMA 1 and DMA 2 will still be able to respond in time, as there are 924 cycles per sample at 18 kHz.
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