gbadev.org forum archive

This is a read-only mirror of the content originally found on forum.gbadev.org (now offline), salvaged from Wayback machine copies. A new forum can be found here.

Beginners > Making my makefile better

#112889 - misterDtD - Thu Dec 21, 2006 5:55 am

I heard makefiles were supposed to make comiling do alot faster, but it doesn't seem faster than using a BATCH file.

So, is it my makefile, if so how could I make it better?

Code:
IN= infile
OUT= outfile

CC= arm-eabi-gcc
OBJCOPY= arm-eabi-objcopy

.PHONY : build
build:
   $(CC) -mthumb-interwork -marm -c $(IN).c
   $(CC) -specs=gba.specs -marm-interwork -marm $(IN).o -o $(IN).elf
   $(OBJCOPY) -v -O binary $(IN).elf $(OUT).gba
   -@gbafix $(OUT).gba

.PHONY : clean
clean:
   @rm -fv $(IN).o
   @rm -fv $(IN).elf

#EOF


~DtD
BTW> Can I make certain files compile in ARM code and the rest in THUMB code? because the only function in my program that needs the ARM code is my interrupt function.

PS> I'm including all my resources (graphics, music, ect.) via "#include" directives, but I heard about linking them in the makefile, how do I do this, is it what's causing the long compile time?

PS2> I'm new to makefiles, so please explain what you post, don't just post a bunch of make "code".

PS3> I saw the make file tutorial in the documentation section, but it's for the old version of DevkitAdv

#112914 - gmiller - Thu Dec 21, 2006 3:37 pm

Your makefile the way I read it will build the code each time you use it even it you do it twice in a row. The way a makefile "speeds" things up is NOT doing things that do not need to be done.

The compilation step generates object files from the source files. The link stage combines the object files into an executable. Now this is a simplified view but works well for makefiles.

You should have a compilation step that generates the object file from the source with the appropriate "dependencies" indicated. This means that if you use the make file twice in a row the makefile can "figure out" that the compile stage does not need to be done. Of course the link stage is dependent on the object files.

The makefile tutorial you mention should apply still, just the names of the utilities to compile and link have changed.

As a brain dead example without regard to the tools here is a very simple makefile. The executable will be made up of three object files each of which has a few special headers in it.

Code:


I = ../include
CC = arm-eabi-gcc
LD = arm-eabi-gcc
CCFLAGS        = -mthumb

# Create general rul to convert a .c to a .o
# $* = name of current prerequisite
.c.o :
   $(CC) -c  -g $(CCFLAGS) -I $(I) $*.c

# Create general rule to convert from .elf to .gba
.elf.gba
         $(OBJCOPY) -v -O binary $*.elf $*.gba

# First label is the default target
all:    foo.gba

# since we have a general rul we can just indicate the out:  in form
foo.gba:    foo.elf

# build foo.elf from the object files, $@ = target name, in this case foo.elf
foo.elf:     foo.o junk.o special.o
       $(CC) -specs=gba.specs -marm-interwork -marm  foo.o junk.o special.o -o $@

# define target foo.o as dependent on foo.c and general.h, use general rule
# for .c to .o
foo.o:  foo.c general.h

# junk has two dependencies and used the general rule
junk.o: junk.c general.h junk.h

# special.o has dependencies by also need special steps to build it
special.o:  special.c general.h special.h
       $(CC) -marm -mthumb-interwork -c $*.c

# clean needs to remove all the object files and ELF files (maybe .gba?)
clean:
   rm -f *.o
        rm -f *.elf




I tried to eye ball this and make sure it was correct as I typed it so I think it is correct. There are more compact ways of doing this but I find this kind of example easier to follow.