#139034 - ingramb - Fri Aug 31, 2007 9:58 pm
From gbatek:
The display controller performs VRAM-reads once every 6 clock cycles, a 1 cycle waitstate is generated if the CPU simultaneously accesses VRAM.
How is a simultaneous defined? If 32k of vram is allocated to a background, and the tiles/map for that background are in the first 16k of vram, will the cpu get waitstates when accessing the second 16k?
Or more generally, does the video controller lock down the entire vram block it needs, or just the portion of the block it is accessing from?
The display controller performs VRAM-reads once every 6 clock cycles, a 1 cycle waitstate is generated if the CPU simultaneously accesses VRAM.
How is a simultaneous defined? If 32k of vram is allocated to a background, and the tiles/map for that background are in the first 16k of vram, will the cpu get waitstates when accessing the second 16k?
Or more generally, does the video controller lock down the entire vram block it needs, or just the portion of the block it is accessing from?