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DS development > How to force a rebuild if makefile changes?

#148999 - Dwedit - Sun Jan 13, 2008 12:14 pm

How do I make it so it rebuilds everything if the makefile is newer than the current output file?
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#149000 - Lick - Sun Jan 13, 2008 12:57 pm

Delete the build directories?
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#149002 - kusma - Sun Jan 13, 2008 1:01 pm

"make clean all" is the "standard" way to force a rebuild with makefiles.

#149004 - Dark Knight ez - Sun Jan 13, 2008 1:28 pm

I think Dwedit means doing this with a rule in the Makefile itself, not having to worry about this himself.
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#149007 - kusma - Sun Jan 13, 2008 2:57 pm

Dark Knight ez wrote:
I think Dwedit means doing this with a rule in the Makefile itself, not having to worry about this himself.

Well, then you'd have to make all targets depend on the makefile, and that's not something I'd recommend for a variety of reasons. What's the big problem with having to make clean manually after you've already done the already manual job of modifying a makefile?

#149018 - nipil - Sun Jan 13, 2008 5:20 pm

IF you're using programmer's notepad, well...
ALT+2, then ALT+1 is *really* fast.
So fast actually that i clean my project a whole too often ;)

#149024 - simonjhall - Sun Jan 13, 2008 6:31 pm

kusma is right - the 'make clean all' thing is pretty standard. Even IDEs like eclipse call make with 'clean all' when it wants to do a rebuild.
However, for the lazy you could always add an extra rule named 'rebuild' that looks a bit like this:

Code:
rebuild:
    $(MAKE) clean
    $(MAKE) all
and then call make rebuild when you want to that.
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#149030 - Peter - Sun Jan 13, 2008 7:52 pm

and if you want to make all targets, -B is your friend:
make --help wrote:

Usage: make [options] [target] ...
Options:
-B, --always-make Unconditionally make all targets.

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#149179 - PypeBros - Wed Jan 16, 2008 1:07 pm

include the makefile in the dependencies of the target ?
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#149196 - Dwedit - Wed Jan 16, 2008 4:06 pm

PypeBros wrote:
include the makefile in the dependencies of the target ?


How do I correctly do this? I'm pretty much a n00b to makefiles.
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#149203 - kusma - Wed Jan 16, 2008 5:59 pm

Dwedit wrote:
How do I correctly do this? I'm pretty much a n00b to makefiles.

First I'd like to warn you a bit: Think about why you're doing this. What problems does it solve? I'm not sure I see this as a very practical thing to spend time on, and it makes the makefiles a bit more cryptic. And I think a simple "make clean" is easy enough to do manually whenever you modify a makefile. But that might just be me.

Anyway, normal make rules are defined like this

Code:
target : dependencies
   commands


What you should do, is append the $(MAKEFILE_LIST), a "magic" variable containing all makefiles (the root makefile plus all included makefiles), to the dependency list.

For example: If your makefile had a rule like this:

Code:
%.o : %.c
   $(COMPILE.c) $(OUTPUT_OPTION) $<

you would want to change it to this:
Code:
%.o : %.c $(MAKEFILE_LIST)
   $(COMPILE.c) $(OUTPUT_OPTION) $<

Simple as that.