#43950 - taichi - Sat May 28, 2005 4:22 pm
does anyone work on a nds web browser??
#43952 - dagamer34 - Sat May 28, 2005 5:23 pm
I don't think there is a TCP/IP stack for the DS yet. I don't even think we know how the wireless hardware works in the first place...
_________________
Little kids and Playstation 2's don't mix. :(
#43999 - linus - Sun May 29, 2005 12:53 am
yeah, wifi functions were being added to a library but i lost track of the thread - anyone got a link / updates on progress
#44010 - elbee - Sun May 29, 2005 10:02 am
| linus wrote: |
| yeah, wifi functions were being added to a library but i lost track of the thread - anyone got a link / updates on progress |
http://forum.gbadev.org/viewtopic.php?t=5555&postdays=0&postorder=asc&start=0
#45233 - miyorni - Wed Jun 08, 2005 9:05 pm
This is what we have from firefly:
CODE
0x4805F80 = WEP KEY 1 (20 bytes)
0x4805FA0 = WEP KEY 2 (20 bytes)
0x4805FC0 = WEP KEY 3 (20 bytes)
0x4805FE0 = WEP KEY 4 (20 bytes)
0x4808018 = mac address (6 bytes)
0x4808020 = BSSID (6 bytes)
0x480802C u16 = retry limit
0x4808040 = power state
0x480808C = beacon period (in millisecs)
0x480808E = DTIM period
0x4808158, 0x480815A and 0x480815E = BBP related
0x480817C, 0x480817E and 0x4808180 = RF related
[19:49] <[firefly]> 0x69 BBP reg values are read from firmware header and used to init the damn thing
[20:01] <[firefly]> http://www.rafb.net/paste/results/QMcOpn28.html
[20:20] <[firefly]> bit 6 of 0x48080BC is preamble type
[21:21] <[firefly]> firmware header offset 0xF2 is a list of 2x 3-byte values for each channel (15 channels?), related to channel frequency
[21:22] <[firefly]> 2x 3-byte RF values
[21:24] <[firefly]> RF_Write( first 3-byte value), RF_Write( next 3-byte value)
[21:26] <[firefly]> I use HEdit Pro, but it's not very good, it has an annoying search bug
[21:27] <[firefly]> firmware header offset 0x154 is a list of 15 1-byte values, also channel frequency related
[21:28] <[firefly]> or 14
[21:28] <[firefly]> offset 0x146 is also a list of 1-byte values
[21:29] <[firefly]> those values (offset 0x146) seem to go into BBP reg 0x1E
[21:29] <[firefly]> the values at offset 0x154 are for RF
[21:34] <[firefly]> firmware header offset 0x44 is a list of 16 2-byte MAC reg values for a list of 16 hardcoded MAC reg addresses
[21:34] <[firefly]> MAC regs related to RX & TX
00000000 64 26 92 49 DC 79 7A 2C 4D 41 43 50 20 00 00 4E
00000010 D6 0C 58 01 B2 2C 06 5F 07 11 05 10 04 FF FF FF
00000020 C0 7F C0 7E 40 7E 9A 35 FF FF 2E CA 38 01 00 00
00000030 00 00 00 00 00 00 XX XX XX XX XX XX FE 3F FF FF
00000040 02 18 0C 01 02 00 17 00 26 00 18 18 48 00 40 48
00000050 58 00 42 00 40 01 64 80 E0 E0 43 24 0E 00 32 00
00000060 F4 01 01 01 6D 9E 40 05 1B 6C 48 80 38 00 35 07
00000070 00 00 00 00 00 00 00 00 B0 00 04 01 D8 FF FF C7
00000080 BB 01 BA 7F 5A 01 3F 01 3F 36 36 00 78 28 55 08
00000090 28 16 00 01 0E 20 02 98 98 1F 0A 08 04 01 00 00
000000A0 00 FF FF FE FE FE FE FC FC FA FA FA FA FA F8 F8
000000B0 F6 A5 12 14 12 41 23 03 04 70 35 0E 16 16 00 00
000000C0 06 01 FF FE FF FF 00 0E 13 00 00 28 1C 00 07 C0
000000D0 00 03 9C 12 28 17 14 BA E8 1A 6F 45 1D FA FF 23
000000E0 30 1D 24 01 00 28 00 00 2C 03 9C 06 22 00 08 6F
000000F0 FF 0D 28 17 14 BA E8 1A 37 17 14 46 17 19 45 17
00000100 14 D1 45 1B 54 17 14 5D 74 19 62 17 14 E9 A2 1B
00000110 71 17 14 74 D1 19 80 17 14 00 00 18 8E 17 14 8C
00000120 2E 1A 9D 17 14 17 5D 18 AB 17 14 A3 8B 1A BA 17
00000130 14 2F BA 18 C8 17 14 BA E8 1A D7 17 14 46 17 19
00000140 FA 17 14 2F BA 18 B7 B7 B7 B7 B7 B8 B8 B8 B8 B8
00000150 B9 B9 BA BA 10 10 10 10 10 10 10 10 10 10 10 10
00000160 10 10 1E FF FF FF FF FF FF FF FF FF FF FF FF FF
00000170 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
00000180 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
00000190 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
000001A0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
000001B0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
000001C0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
000001D0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
000001E0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
000001F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
offset length description
------ ------ -----------
0036 0006 mac address
003C 0002 list of enabled channels and'ed with 0x7FFE, each bit represents one channel
003E 0002
0040 0001 ?
0041 0001 ?
0042 0001 ?
0043 0001 ?
0044 0020 list of 16 2-byte MAC reg values for a list of 16 hardcoded MAC reg addresses (see list below) related to RX & TX
0064 0069 list of 1-byte BBP reg values for BBP regs 0..x (reg++), this area is checksummed
00CE ? list of 1-byte RF values
00F2 0054 list of 2x 3-byte RF values for each channel (15 channels?), related to channel frequency, RF_Write( first 3-byte value), RF_Write( next 3-byte value)
0146 000E list of 1-byte BBP reg values, seem to go into BBP reg 0x1E
0154 000E/F list of 14/15 1-byte RF values, also channel frequency related, only lower 5 bits are used
0044 - list of MAC regs (base 0x04808000)
0x146, 0x148, 0x14A, 0x14C, 0x120, 0x122, 0x154, 0x144, 0x130, 0x132, 0x140, 0x142, 0x038, 0x124, 0x128 0x150
void InitMac()
{
*(u16*)(0x04808000 + 0x004) = 0;
*(u16*)(0x04808000 + 0x008) = 0;
*(u16*)(0x04808000 + 0x00A) = 0;
*(u16*)(0x04808000 + 0x012) = 0;
*(u16*)(0x04808000 + 0x010) = 0xFFFF;
*(u16*)(0x04808000 + 0x254) = 0;
*(u16*)(0x04808000 + 0x0B4) = 0xFFFF;
*(u16*)(0x04808000 + 0x080) = 0;
*(u16*)(0x04808000 + 0x02A) = 0;
*(u16*)(0x04808000 + 0x028) = 0;
*(u16*)(0x04808000 + 0x0E8) = 0;
*(u16*)(0x04808000 + 0x0EA) = 0;
*(u16*)(0x04808000 + 0x0EE) = 1;
*(u16*)(0x04808000 + 0x0EC) = 0x3F03;
*(u16*)(0x04808000 + 0x1A2) = 1;
*(u16*)(0x04808000 + 0x1A0) = 0;
*(u16*)(0x04808000 + 0x110) = 0x0800;
*(u16*)(0x04808000 + 0x0BC) = 1;
*(u16*)(0x04808000 + 0x0D4) = 3;
*(u16*)(0x04808000 + 0x0D8) = 4;
*(u16*)(0x04808000 + 0x0DA) = 0x0602;
*(u16*)(0x04808000 + 0x076) = 0;
}
void RF_Write( u32 value)
{
// wait while busy
while ((*(u16*)0x04808180) & 1);
// write value
*(u16*)(0x0480817C + 2) = (u16)(value >> 0);
*(u16*)(0x0480817C + 0) = (u16)(value >> 16);
// wait while busy
while ((*(u16*)0x04808180) & 1);
}
u16 BBP_Read( u8 reg)
{
// wait while busy
while ((*(u16*)0x0480815E) & 1);
// set reg number
*(u16*)0x04808158 = 0x6000 | reg;
// wait while busy
while ((*(u16*)0x0480815E) & 1);
// return value
return *(u16*)0x0480815C;
}
// returns 0 (ok) or -1 (timeout)
u32 BBP_Write( u8 reg, u16 value)
{
u32 try;
// wait while busy
try = 0;
while ((*(u16*)0x0480815E) & 1) if (try++ > 10000) return 0xFFFFFFFF;
// write value & set reg number
*(u16*)0x0480815A = value;
*(u16*)0x04808158 = 0x5000 | reg;
// wait while busy
try = 0;
while ((*(u16*)0x0480815E) & 1) if (try++ > 10000) return 0xFFFFFFFF;
// exit
return 0;
}