#11420 - poslundc - Mon Oct 06, 2003 2:52 am
The GBA has a 3-stage pipleline. Do branch instructions flush the pipeline, or can you do creative assembly branching (like you can in MIPS) so that the instruction immediately following a branch instruction gets executed?
For that matter, will -O3 on gcc do that for me? :)
(I'm writing a somewhat time-critical function and trying to weigh the costs and benefits of having greater or fewer branch instructions in it...)
Thanks,
Dan.
#11422 - tepples - Mon Oct 06, 2003 5:43 am
The ARM architecture does not have MIPS-style delay slots. Taken branches on ARM7 cores flush the pipeline, costing two cycles. You'll want to use conditional execution to reduce forward branches and loop unrolling to reduce backward branches.
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#11426 - poslundc - Mon Oct 06, 2003 4:29 pm
| tepples wrote: |
| The ARM architecture does not have MIPS-style delay slots. Taken branches on ARM7 cores flush the pipeline, costing two cycles. You'll want to use conditional execution to reduce forward branches and loop unrolling to reduce backward branches. |
Conditional execution is only available in ARM, not Thumb, however?
Therefore any code generated by gcc at any optimization level will, by default, branch instead of using conditional execution, if I am not mistaken.
That sucks.
Dan.
#11433 - tepples - Mon Oct 06, 2003 7:58 pm
If you're getting to the point where you count cycles, it may be time to put ARM code in IWRAM.
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-- I think he moved to Tilwick.
#11438 - tom - Tue Oct 07, 2003 12:31 am
| poslundc wrote: |
| Therefore any code generated by gcc at any optimization level will, by default, branch instead of using conditional execution, if I am not mistaken. |
That is, any code compiled as thumb =)