#18869 - nadia - Wed Apr 07, 2004 2:58 pm
Hi everybody,
I am trying to learn how to calculate how long a sequential code will take to execute in cycles. In ARM docs, I found a timing table for all usual operations but when computing a global execution time on a piece of code, it wasn't accurate.
Someone can help me!!
if someone encountered a precise emulator that gives execution time, please send me th URL.
#18870 - Lupin - Wed Apr 07, 2004 3:30 pm
For me this smells like an ASM topic :P
Well, calculating cycle times is a bit tricky (I did not really understand the docs explanations about this).
If you only need it to "profile" your code you can also assume that each instruction takes 1-2 cycles (I think mul takes ~5 cycles), so basically every instruction takes the same time, there are no huge differences. I don't think that optimizing code cycle by cycle is very good, rather try to cut down the count of instructions in your code...
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#18872 - torne - Wed Apr 07, 2004 4:12 pm
The No$ documentation has the correct cycle timings for instructions in terms of S and N times, but these only work for single instructions in isolation. You need to consider pipelining effects to notice when instruction fetches collide with memory read/writes (which causes the instruction fetch to be delayed until the memory access has completed). Basically, you can't work it out by hand for any code longer than a few instructions (unless you are very patient) and there are no emulators which are cycle-accurate (none emulate the pipeline at all, so they never have memory bus collisions).
#18880 - poslundc - Wed Apr 07, 2004 7:04 pm
The length of a sequential cycle depends on what area of memory the instruction is being read from. From IWRAM this is 1 cycle, from EWRAM it's 3 cycles for Thumb instructions and 6 for ARM instructions, and from normal ROM it can vary depending on the type of instruction, waitstate settings, and whether the prefetch is turned on, but in the general case about 2 cycles for Thumb instructions and 4 for ARM instructions. (Note that those are sequential cycles; non-sequential cycles in ROM take a big performance hit.)
And as torne mentioned, there is also the pipeline to consider.
Dan.