#3477 - Drago - Tue Feb 25, 2003 6:06 pm
Hello,
I've been playing around with DMA HBlank transfers, and I've found the following issues:
GBATEK info says, under 'LCD Dimensions and Timings' section:
Note that no H-Blank interrupts are generated within V-Blank period.
Also from GBATEK, in the section explaining the DMA repeat bit:
The transfer will be repeated forever, until it gets stopped by software.
VisualBoy (v1.4) behaviour is:
H-Blank interrupts are generated within V-Blank period.
The DMA HBlank transfer is stopped at VBlank.
And my tests on the hardware tell me that:
H-Blank interrupts ARE generated within V-Blank period (agrees VBoy).
The DMA HBlank transfer is NOT stopped at VBlank (agrees GBATEK).
Can anybody confirm the hardware behaviour?
Thanks.
I've been playing around with DMA HBlank transfers, and I've found the following issues:
GBATEK info says, under 'LCD Dimensions and Timings' section:
Note that no H-Blank interrupts are generated within V-Blank period.
Also from GBATEK, in the section explaining the DMA repeat bit:
The transfer will be repeated forever, until it gets stopped by software.
VisualBoy (v1.4) behaviour is:
H-Blank interrupts are generated within V-Blank period.
The DMA HBlank transfer is stopped at VBlank.
And my tests on the hardware tell me that:
H-Blank interrupts ARE generated within V-Blank period (agrees VBoy).
The DMA HBlank transfer is NOT stopped at VBlank (agrees GBATEK).
Can anybody confirm the hardware behaviour?
Thanks.