#111246 - Ant6n - Tue Dec 05, 2006 4:51 am
in gbatek the waitcnt registers is explained, allowing the user to set waitstates of 4,3,2,8 cycles for nonsequential and 2,1 for sequential reads. Is there a way to find out which speeds a rom supports, so that i can write a program that runs on all sorts of flash cards alwas at the fastest possible speed? (i.e. if i set the speed to high, will a rom-access return grabrage?)
#111387 - tepples - Wed Dec 06, 2006 4:14 am
All GBA flash cards (except Visoly's earliest products) support 3/1 wait state. Some do not support the fastest 2/1 setting, which means some demos by Shitfaced Clowns need a special "lamer version" version set to 3/1.
The obvious test is copy the first 4 KB of the ROM to a buffer in RAM backwards byte-by-byte using the power-on default 4/2 wait state, do the same in 2/1 wait state, and compare the results. Using backwards byte-by-byte is intended to exercise the nonsequential reads as much as possible, as they're the only significant difference among flash cards.
But I will warn you, as someone warned me when the undocumented EWRAM overclocking register was discovered, that the fastest supported speed might vary over time because it varies with temperature. Assume 3/1 to be safe.
_________________
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#111397 - Ant6n - Wed Dec 06, 2006 5:56 am
thanks for the rply.
cool, i can run ewram at 1 cycle sequential? -> that's as fast as internal working ram (well, for 16bits). Maybe its possible to write a tool that can read the temperature of the gba hardware based on readerrors :P
I am still a little unclear though. 1 waitstate means that an access will take 2 cycles, yes? And if all memory has at least 1 waitstate according to the specs, why do i sometimes read people talk about 0 waitstates?
#111509 - tepples - Thu Dec 07, 2006 4:41 am
| Ant6n wrote: |
thanks for the rply.
cool, i can run ewram at 1 cycle sequential? -> that's as fast as internal working ram (well, for 16bits) |
IWRAM is 0 wait state. VRAM is between 0 and 1 wait state; as I understand it, the VRAM timing depends on when and how you access it.
| Quote: |
| 1 waitstate means that an access will take 2 cycles, yes? And if all memory has at least 1 waitstate according to the specs, why do i sometimes read people talk about 0 waitstates? |
0 wait states means the access happens in 1 cycle, as is the case with IWRAM and (sometimes) VRAM.
_________________
-- Where is he?
-- Who?
-- You know, the human.
-- I think he moved to Tilwick.