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ASM > Nested interrupts, "Undefined" instruction?

#177835 - WriteASM - Sun Mar 31, 2013 12:54 pm

Does anyone know if nested interrupts are possible when the CPU is in IRQ mode? In my experience, if the CPU gets hung in IRQ mode, then interrupts don't work. GBA PanDocs say, "If user wants to allow nested interrupts, save SPSR_irq, then enable IRQs." Perhaps the interrupt handler needs to be in a different CPU mode? If so, how do I ensure that the CPU runs the ARM subset when switching to modes that might have been running THUMB?

Also, can the "ARM7TDMI Undefined Instruction" trap be used in the GBA? According to VisualBoyAdvance, the BIOS has a branch instruction at the trap's address of $00000004, but the GBA documentation that I have doesn't mention any interface for the trap. If the undefined instruction trap is useable, can the unused bits in the instruction be set to a custom value? ("User SWI")

Thanks for any help.

#177842 - WriteASM - Fri Apr 05, 2013 12:50 pm

OK, I've figured it out. To enable nested interrupts, the "IRQ" disable bit in the CPSR must be cleared in the interrupt service routine. (That makes a third interrupt enable.)

And the "Undefined instruction" trap is reserved for Nintendo's hardware debugger. Oh, well...
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