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ASM > ARM conditional field

#17343 - DarkPhantom - Sat Mar 06, 2004 5:46 pm

Quick question since I can't find the answer in any of my ARM documentation. How costly are conditional instructions that don't execute? I mean do instructions that fail their conditional field still use the cycles that they would have had they executed? I'm just woundering where it becomes more desireable to use a branch as opposed to a block of conditional instructions.

For example, I wrote this "if else" block not that long ago:

orrs r8, r8, r8

mulne r12, r11, r1
addne r12, r12, r0, LSL #1

muleq r12, r11, r0
addeq r12, r12, r1, LSL #1

would that be more desireable than

orrs r8, r8, r8
beq else

mul r12, r11, r1
add r12, r12, r0, LSL #1
b endif

else:
mul r12, r11, r0
add r12, r12, r1, LSL #1

endif:

I think the first way is much easier to follow (when its commented). Of course, I'm one of those problem programmer's who wants to "conserve" labels. :P
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#17346 - Miked0801 - Sat Mar 06, 2004 6:44 pm

1 cycle per instruction not executed on a conditional.

#17356 - torne - Sat Mar 06, 2004 8:48 pm

You don't have to conserve labels; use local ones. =)

#17358 - jma - Sat Mar 06, 2004 9:20 pm

Unless you have a lot of instructions between your IF/ELSE/ENDIF, it is always better to use the condition codes. This is because branching *may* cause the pipeline to be flushed.

The cycles spent not executing opcodes is minimal to the time it takes to refill the pipeline and continue executing again. This is especially true in this situation, where a branch will execute no matter what.

Jeff
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#17359 - Miked0801 - Sat Mar 06, 2004 9:34 pm

Um, what pipeline?

3 cycles (in IWRAM) to branch means that you break even on cycles if you need to skip 3 opcodes, but lose 4 bytes due ot the extra opcode on ROM. If you need to skip 4, use a branch.

#17361 - torne - Sat Mar 06, 2004 10:03 pm

jma wrote:
Unless you have a lot of instructions between your IF/ELSE/ENDIF, it is always better to use the condition codes. This is because branching *may* cause the pipeline to be flushed.

Technically yes, except the ARM7 pipeline is only three stages long (fetch/decode, execute, memory access), and thus a branch causes only one cycle of penalty in addition to the time required to do a non-consecutive fetch on the next instruction (which is the same as consecutive if not executing from ROM).