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ASM > How does it compare to intel's assembly?

#30715 - sinstone - Fri Dec 03, 2004 8:54 pm

hey all,

im taking an Intel assembly course atm and I was wondering how the GBA's assembly language differs from that of Intel? what are the names of the registers and what are they used for? where can i get some tutorials?

thanks in advance guys

#30716 - Lupin - Fri Dec 03, 2004 9:00 pm

http://k2pts.home.comcast.net/gbaguy/oldgba/gbaasm.htm
http://k2pts.home.comcast.net/gbaguy/gbaasm.htm

registers are named r0-r15.

Copied from the tutorial:

r0-r12: GPRs (General Purpose Registers)

r13: Typically used as a stack pointer, if you don't use the stack (small demo or something, then this can be considered a GPR).

r14: Link register, can be used as a GPR, but its main purpose is to hold return addresses for the Branch and Link Instruction (a sub-routine call).

r15: PC register, holds the address +8 of the current instruction (ARM7 has a 3 stage pipeline, so if you read PC, it will have the address of 2 instructions a head of the one you used to read it).
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#30736 - pyros - Sat Dec 04, 2004 1:45 am

quite a few differences, but i found the change from intel-to-arm quite easy to make, mainly thanks to having more registers.

actually, there are plenty of differences including:

negetive(ish):

far fewer commands

no 'div' :(

generally slower. mul's can significantly affect execution speed.


positive(ish):
conditional instruction execution (most instructions can be given conditions)

more registers to use

less backwards compatibility (bit more simple to learn)

can use arm or thumb (can be useful, but not necesseraly on gba)

better stack control???

shifts can be appended to other instructions



BUT the best way is to learn the differences as you come across them in tutorials.

Oh, and download the instruction reference from www.arm.com

There is a datasheet at:
http://www.arm.com/pdfs/QRC0001H_rvct_v2.1_arm.pdf
but not all the instructions apply to the arm7tdmi that the GBA uses.

#30756 - sgeos - Sat Dec 04, 2004 7:45 am

pyros wrote:
far fewer commands

I'd call this positive.

-Brendan

#30766 - Lupin - Sat Dec 04, 2004 12:54 pm

positive? Well, i guess MMX type instructions would be quite usefull on any CPU =P

But the ARM CPU is a RISC CPU (reduced instruction set computer).
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#30769 - keldon - Sat Dec 04, 2004 2:38 pm

A few of the MMX instructions would be useful, besides we only need a few of them.

#30796 - sgeos - Sat Dec 04, 2004 8:39 pm

Write subroutines that add the MMX functionality?

-Brendan

#30826 - sinstone - Sun Dec 05, 2004 7:36 am

thanks for the info guys

good reading material for the holidays :P

intel is evil!

#30828 - keldon - Sun Dec 05, 2004 8:52 am

sgeos wrote:
Write subroutines that add the MMX functionality?

-Brendan

Obviously they could be written. But the point of it is the speed that it executes. For example you can do 4 multiplies in one instruction. And the pipeline can allow you to get so many of them is so few ticks for what you're doing.

#30932 - pan69 - Mon Dec 06, 2004 10:19 am

Quote:
But the ARM CPU is a RISC CPU (reduced instruction set computer).


The reduced, in RISC, has nothing to do with the number of instructions in the instruction set. The reduced aimes at the reduced in complexity rather the number of instructions. For example the are plenty of CISC (complex instruction set computer) processors out there with less instructions than an ARM7TDMI.

- Pan

#31329 - Miked0801 - Fri Dec 10, 2004 3:26 am

I know both and would always rather code on ARM, MIPS or even Z80 over x86. There are just too many things to remeber on which silly commands work on which registers, plus it is (was) very register starved.

#31338 - jma - Fri Dec 10, 2004 6:15 am

Lupin wrote:
But the ARM CPU is a RISC CPU (reduced instruction set computer).


Just as an interesting tidbit of information for those that might care: the x86 is a RISC processor [internally]. The exposed instruction set that has been passed down through the ages is translated into a RISC instruction set before executed.

Addendum: I should add the reasoning behind this... Intel regularly checks with the most common commercial C compiler manufacturers (eg, Microsoft and Metroworks) and creates programs for them to compile. They do this to see which instruction combinations are the most commonly generated by the compilers and those are the instructions that are optimized for the next revision of their processor.

A while ago, a pattern began to emerge that the most common instructions were typically those of the general RISC design. So, instead of trying to optimize a "dead end", they adopted and translate. Only the internal RISC design is optimized.

It is also quite amazing that Intel has managed to keep (relatively) the same instruction set for so long. We're running on machines that were originally designed to run automatic bottle openers and toasters. :)

http://en.wikipedia.org/wiki/RISC
http://topcc.org/articles/history.html#B

Miked0801 wrote:
(about the x86) ...plus it is (was) very register starved

Pop quiz: anyone care to take a guess how many registers are on a modern Pentium chip?

Jeff
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#31348 - tepples - Fri Dec 10, 2004 7:43 am

Excluding specialized registers such as those associated with debugging, interrupt handling, and virtual memory, somebody familiar with the ARM architecture would count nine registers on the x86: EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP, and EIP, which correspond roughly to r0, r1, r2, r3, r4, r5, r6, sp, and pc of Thumb.
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#31351 - jma - Fri Dec 10, 2004 8:53 am

Yes, I should have mentioned that I'm not counting all the lovely specialized registers used for branch predicting, etc. (otherwise the count would be in the hundreds). Also, I'm not counting the 8 floating pointer registers, which are really on the x87 FPU.

Here's a hint, though: register renaming.

Jeff
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#31358 - pan69 - Fri Dec 10, 2004 11:43 am

Quote:
the x86 is a RISC processor [internally]


Yeah, right! Which processor isn't... That's the whole point of being RISC, it's not RISC only internally but it's RISC the whole way and that is makes the difference between CISC and RISC.

- Pan

#31378 - poslundc - Fri Dec 10, 2004 5:58 pm

pan69 wrote:
Quote:
the x86 is a RISC processor [internally]


Yeah, right! Which processor isn't... That's the whole point of being RISC, it's not RISC only internally but it's RISC the whole way and that is makes the difference between CISC and RISC.


Um... no?

Dan.

#64887 - Dr_Kachu - Wed Dec 28, 2005 2:20 am

x86 still uses segmented memory?
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