#12593 - DiscoStew - Tue Nov 18, 2003 11:19 pm
Just a few questions...
How much of a pause would there be if the entire OAM memory (32K) was DMAed over itself? Obviously this is pointless to do, but it is relevant to DMAing a large chunk from one point in OAM memory to another. I'm not talking about from ROM, just within OAM memory.
Where does OAM/Tile memory lie? Is it in internal RAM, external RAM, or somewhere else? Would it be possible to use DMA0 instead of DMA3 in conjunction with OAM/Tile memory? This relates to the first question addressing speed when copying within the same area of memory.
thx
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#12597 - tepples - Tue Nov 18, 2003 11:54 pm
The OAM is not 32 KiB. The 32 KiB area from 0x06010000 to 0x06017fff is called "sprite cel VRAM." OAM is the 1 KiB display list that occupies 0x07000000 to 0x070003ff.
Yes, you can fit a 32 KiB copy from ROM to VRAM within one vblank. The vblank is 1232*68 = 83776 cycles long. A DMA3 copy from ROM to VRAM at typical ROM wait state settings (3/1) takes 3 cycles per 2 bytes, or 49152 cycles to copy all of VRAM. A DMA3 copy from EWRAM to VRAM is slower, but not by much: 4 cycles per 2 bytes, or 65536 cycles total.
To learn more about continuous copying to sprite cel VRAM, read my white paper, entitled "Managing Sprite Cel VRAM on the Game Boy Advance".
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#12628 - DiscoStew - Wed Nov 19, 2003 10:56 pm
Whoops, my bad. It's VRAM, not OAM (Object Attribute Memory).
I'm glad to see that it does well with ROM to VRAM transfers, but my question was taking the entire sprite cel VRAM, and DMAing over itself right back to where it was stored. How many cycles would that take to DMA VRAM to VRAM?
I'm curious because I plan on organizing sprites according to objects that I have, and when 1 object is removed in the middle of a group, then the sprite image associated with that object is dereferenced and all the sprite images after that image will move up the line over where that previous image was, leaving all the empty/unused space at the end of VRAM. It's all about organization. It's important to my design.
Also unanswered, what about using DMA0 with VRAM-to-VRAM coping? I'm all about speed. I doubt it's possible since DMA0 is associated with IRAM, which (if I'm correct) is on the CPU, but I'd like another person's opinion about it.
Sorry if I sound desperate or anything like that. I've been on and off with GBA programming, and I'm trying to get back in the groove.
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#12634 - tepples - Thu Nov 20, 2003 12:38 am
Any DMA channel will work VRAM-to-VRAM, and because VRAM is zero wait state during vblank, copies should in fact be very fast (32 KiB from VRAM to VRAM in 32768 cycles).
By your talk of compaction, it seems you're worried more about external fragmentation than anything else. You can get around external fragmentation by using small allocation unit sizes, such as the 512 byte VRAM allocation that my white paper suggests. The FAT (file allocation table) used in MS-DOS is an example of this.
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#12637 - DiscoStew - Thu Nov 20, 2003 1:15 am
thx for the info.
The external fragmentation that you speak of is not a problem for me. I've got my handles and rereferencing worked out so that all unused space in VRAM is all at the end and that everything is linked correctly. My worry was more of making sure that my process of organizing objects (or sprites) wouldn't slow down my games so much that it would be noticable.
Again, thx
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#12644 - ampz - Thu Nov 20, 2003 11:31 am
| tepples wrote: |
| Yes, you can fit a 32 KiB copy from ROM to VRAM within one vblank. The vblank is 1232*68 = 83776 cycles long. A DMA3 copy from ROM to VRAM at typical ROM wait state settings (3/1) takes 3 cycles per 2 bytes, or 49152 cycles to copy all of VRAM. |
I can't make sense of your math...
You are saying that a 32bit word transfer from ROM to VRAM takes 6 cycles.
Let's see, the first read from ROM takes 4 cycles at 3/1 waitstates. The second read takes 2 cycles. Then there is the 32bit write to VRAM. VRAM is 16bit, that's 2 cycles. I get a total of 8 cycles.
The only way I can get it to 6 cycles is if all ROM reads (eqcept the very first one) are sequential. I don't think that's the case during a DMA transfer. Perhaps if prefetch is turned on, but then again, someone said prefetch only works for instructions, not data transfers.
#12646 - tepples - Thu Nov 20, 2003 2:11 pm
| ampz wrote: |
| The only way I can get it to 6 cycles is if all ROM reads (eqcept the very first one) are sequential. I don't think that's the case during a DMA transfer. |
My DMA speed test program running on my GBA tells me that ROM reads under normal DMA conditions (increasing source address) are in fact sequential after the first.
Prefetch for code transfers works only to make sequential reads of code from ROM even faster.
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-- I think he moved to Tilwick.
#12647 - ampz - Thu Nov 20, 2003 2:29 pm
In theory, a prefetch feature could make it possible for a DMA transfer to "read while write". The DMA hardware can write to VRAM while the prefetch reads the next word from ROM. But that's just theory. I guess this prefetch feature only works with the instruction pipeline.