Memory-Mapped Hardware Registers

The following section describes the function of each of the memory-mapped addresses in IO RAM. The register naming scheme is based on a variant of the popular gba.h by Eloist (specifically, that used by Uze in the examples on his Audio Advance site).

The notation for each entry is as follows:

                           R       <- 'R' means "Read Only", 'W' means "Write Only"
F E D C  B A 9 8  7 6 5 4  3 2 1 0   <- These are the bits
W V U S  L K J I  F D B A  C M M M   <- These letters are used in the key.
                                     Entries marked with an 'X' usually 
                                     serve no function, are unwriteable,
                                     and remain at 0.


0x04000000 - 0x04000054 - Graphics Hardware Registers

0x04000000 - REG_DISPCNT (The display control register)

                           R
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
W V U S  L K J I  F D B A  C M M M 
BitsDescription
0-2 (M)The video mode. See video modes for details.
3 (C)Game Boy Color mode. Read only - should stay at 0.
4 (A)This bit controls the starting address of the bitmap in bitmapped modes and is used for page flipping. See the description of the specific video mode for details.
5 (B)Force processing during hblank. Setting this causes the display controller to process data earlier and longer, beginning from the end of the previous scanline up to the end of the current one. This added processing time can help prevent flickering when there are too many sprites on a scanline.
6 (D)Sets whether sprites stored in VRAM use 1 dimension or 2.
0 = 2D: each row of tiles is stored 32x64 bytes in from the start of the previous row.
1 = 1D: tiles are are stored sequentially.
7 (F)Force the display to go blank when set. This can be used to save power when the display isn't needed, or to blank the screen when it is being built up (such as in mode 3, which has only one framebuffer). On the SNES, transfers rates to VRAM were improved during a forced blank; it is logical to assume that this would also hold true on the GBA.
8 (I)If set, enable display of BG0.
9 (J)If set, enable display of BG1.
A (K)If set, enable display of BG2.
B (L)If set, enable display of BG3.
C (S)If set, enable display of sprites.
D (U)Enable Window 0
E (V)Enable Window 1
F (W)Enable Sprite Windows

0x04000004 - REG_DISPSTAT

                             R R R
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
T T T T  T T T T  X X Y H  V Z G W 
BitsDescription
0 (W)V Refresh status. This will be 0 during VDraw, and 1 during VBlank. VDraw lasts for 160 scanlines; VBlank follows after that and lasts 68 scanlines. Checking this is one alternative to checking REG_VCOUNT.
1 (G)H Refresh status. This will be 0 during HDraw, and 1 during HBlank HDraw lasts for approximately 1004 cycles; HBlank follows, and lasts approximately 228 cycles, though the time and length of HBlank may in fact vary based on the number of sprites and on rotation/scaling/blending effects being performed on the current line.
2 (Z)VCount Triggered Status. Gets set to 1 when a Y trigger interrupt occurs.
3 (V)Enables LCD's VBlank IRQ. This interrupt goes off at the start of VBlank.
4 (H)Enables LCD's HBlank IRQ. This interrupt goes off at the start of HBlank.
5 (Y)Enable VCount trigger IRQ. Goes off when VCount line trigger is reached.
8-F (T)Vcount line trigger. Set this to the VCount value you wish to trigger an interrupt.

0x04000006 - LCY / REG_VCOUNT (Read Only)

This location stores the current y location of the LCD hardware. It is incremented as the lines are drawn. The 160 lines of display are followed by 68 lines of Vblank period, before the whole thing starts again for the next frame. Waiting for this register to reach 160 is one way to synchronize a program to 60Hz.

0x04000008 - 0x0400001E - Background Registers

0x04000008 - REG_BG0CNT
0x0400000A - REG_BG1CNT
0x0400000C - REG_BG2CNT
0x0400000E - REG_BG3CNT

These addresses set up the four background layers. The format is:

    ?             
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
Z Z V M  M M M M  A C X X  S S P P 
BitsDescription
0-1 (P)

Priority: 00 = highest, 11 = lowest

Priorities are ordered as follows:

"Front" 
1. Sprite with priority 0
2. BG with priority 0
3. Sprite with priority 1
4. BG with priority 1
5. Sprite with priority 2
6. BG with priority 2
7. Sprite with priority 3
8. BG with priority 3
9. Backdrop
"Back"

When multiple backgrounds have the same priority, the order from front to back is: BG0, BG1, BG2, BG3. Sprites of the same priority are ordered similarly, with the first sprite in OAM appearing in front.

2-3 (S)Starting address of character tile data
Address = 0x06000000 + S * 0x4000
6 (C)Mosiac effect - 1 on, 0 off
7 (A)Color palette type -
1 - standard 256 color pallete
0 - each tile uses one of 16 different 16 color palettes (no effect on rotates/scale backgrounds, which are always 256 color)
8-C (M)Starting address of character tile map Address = 0x06000000 + M * 0x800
D (V)Screen Over. Used to determine whether rotational backgrounds get tiled repeatedly at the edges or are displayed as a single "tile" with the area outside transparent. This is forced to 0 (read only) for backgrounds 0 and 1 (only).
E-F (Z)

Size of tile map

For "text" backgrounds:

00 = 256x256 (32x32 tiles)
01 = 512x256 (64x32 tiles)
10 = 256x512 (32x64 tiles)
11 = 512x512 (64x64 tiles)

For rotational backgrounds:

00 = 128x128 (16x16 tiles)
01 = 256x256 (32x32 tiles)
10 = 512x512 (64x64 tiles)
11 = 1024x1024 (128x128 tiles)

0x04000010 - REG_BG0HOFS Horizontal scroll co-ordinate for BG0 (Write Only)
0x04000012 - REG_BG0VOFS Vertical scroll co-ordinate for BG0 (Write Only)
0x04000014 - REG_BG1HOFS Horizontal scroll co-ordinate for BG1 (Write Only)
0x04000016 - REG_BG1VOFS Vertical scroll co-ordinate for BG1 (Write Only)
0x04000018 - REG_BG2HOFS Horizontal scroll co-ordinate for BG2 (Write Only)
0x0400001A - REG_BG2VOFS Vertical scroll co-ordinate for BG2 (Write Only)
0x0400001C - REG_BG3HOFS Horizontal scroll co-ordinate for BG3 (Write Only)
0x0400001E - REG_BG3VOFS Vertical scroll co-ordinate for BG3 (Write Only)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X X X  X X S S  S S S S  S S S S 
0-9 (S) = Scroll value (pixels) 

These registers are only effective for text backgrounds; they set the pixel that is displayed in the top left hand corner of the GBA's display. In other words, a value of -5, -5 puts the upper left hand corner of your background at x=5,y=5. All four BG planes wrap when they reach their right or bottom edges.


0x04000020 - 0x04000026 / 0x04000030 - 0x04000036 - Background Rotation/Scaling Registers (Write Only)

These registers affect the translation, rotation, and scaling of tile-based rotate/scale backgrounds as well as the bitmapped backgrounds (which should be treated as BG2 for this purpose). The function of these registers is very hard to describe in words but easy to see the effects of on screen. I highly recommend checking out Stephen Stair's RSDemo - it lets you see the contents of the regs as you modify them as well as the effect they have on the background. Should also be somewhat useful for figuring out sprite rotation and scaling.

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
S I I I  I I I I  F F F F  F F F F 
BitsDescription
0-7 (F)Fraction
8-E (I)Integer
F (S)Sign bit

These registers apply only to Rotate/Scale backgrounds. Individual descriptions follow:

0x04000020 - REG_BG2PA (BG2 Read Source Pixel X Increment) (Write Only)
0x04000030 - REG_BG3PA (BG3 Read Source Pixel X Increment) (Write Only)

The effect of these registers is to scale the background (relative to the upper left corner) in the x direction by an amount equal to 1/(register value).

0x04000022 - REG_BG2PB (BG2 Write Destination Pixel X Increment) (Write Only)
0x04000032 - REG_BG3PB (BG3 Write Destination Pixel X Increment) (Write Only)

The effect of these registers is to shear the x coordinates of the background over y, relative to the upper left corner. A value of 0 will result in no shearing, a value of 1.00 will make the background appear to be sheared left as you go down the screen, and a value of -1 will make the background appear sheared right as you go down the screen.

0x04000024 - REG_BG2PC (BG2 Read Source Pixel Y Increment) (Write Only)
0x04000034 - REG_BG3PC (BG3 Read Source Pixel Y Increment) (Write Only)

The effect of these registers is to shear the y coordinates of the background over x, relative to the upper left corner. A value of 0 will result in no shearing, a value of 1.00 will make the background appear to be sheared upwards to the right, and a value of -1 will make the background appear sheared downwards and to the right.

0x04000026 - REG_BG2PD (BG2 Write Destination Pixel Y Increment) (Write Only)
0x04000036 - REG_BG3PD (BG3 Write Destination Pixel Y Increment) (Write Only)

The effect of these registers is to scale the background in the y direction (relative to the upper left corner) by an amount equal to 1/(register value).


0x04000028 - REG_BG2X (X Coordinate for BG2 Rotational Background) (Write Only)
0x04000038 - REG_BG3X (X Coordinate for BG3 Rotational Background) (Write Only)

0x0400002C - REG_BG2Y (Y Coordinate for BG2 Rotational Background) (Write Only)
0x0400003C - REG_BG3Y (Y Coordinate for BG3 Rotational Background) (Write Only)

31 30 29 28  27 26 25 24  23 22 21 20  19 18 17 16  15 14 13 12  11 10 9 8  7 6 5 4  3 2 1 0
X  X  X  X   S  I  I  I   I  I  I  I   I  I  I  I   I  I  I  I   I  I  I I  F F F F  F F F F 
BitsDescription
0-7(F)Fraction
8-26(I)Integer
27(S)Sign bit

These registers define the location of the pixel that appears at 0,0. They are very similar to the background scrolling registers, REG_HOFS and REG_VOFS, which become disabled when a rotate/ scale background is in use.


0x04000040 - 0x0400004A - Windowing Registers

0x04000040 - REG_WIN0H Window 0 X Coordinates) (Write Only)
0x04000042 - REG_WIN1H Window 1 X Coordinates) (Write Only)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
L L L L  L L L L  R R R R  R R R R 
BitsDescription
0-7 (R)X coordinate for the rightmost side of the window
8-F (L)X coordinate for the leftmost side of the window

0x04000044 - REG_WIN0V Window 0 Y Coordinates) (Write Only)
0x04000046 - REG_WIN1V Window 1 Y Coordinates) (Write Only)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
T T T T  T T T T  B B B B  B B B B 
BitsDescription
0-7 (B)Y coordinate for the bottom of the window
8-F (T)Y coordinate for the top of the window

0x04000048 - REG_WININ (Inside Window Settings)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X T S  R Q P O  X X L K  J I H G 
BitsDescription
0 (G)BG0 in win0
1 (H)BG1 in win0
2 (I)BG2 in win0
3 (J)BG3 in win0
4 (K)Sprites in win0
5 (L)Blends in win0
8 (O)BG0 in win1
9 (P)BG1 in win1
A (Q)BG2 in win1
B (R)BG3 in win1
C (S)Sprites in win1
D (T)Blends in win1

0x0400004A - REG_WINOUT (Outside Window and Sprite Window)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X T S  R Q P O  X X L K  J I H G 
BitsDescription
0 (G)BG0 outside
1 (H)BG1 outside
2 (I)BG2 outside
3 (J)BG3 outside
4 (K)Sprites in win0
5 (L)Blends in win0
8 (O)BG0 in sprite win
9 (P)BG1 in sprite win
A (Q)BG2 in sprite win
B (R)BG3 in sprite win
C (S)Sprites in sprite win
D (T)Blends in sprite win



0x0400004C - 0x04000054 - Effects Registers

0x0400004C - REG_MOSAIC (Write Only)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
V V V V  U U U U  J J J J  I I I I 
BitsDescription
0-3 (I)BG X Size
4-7 (J)BG Y Size
8-B (U)Sprite X Size
C-F (V)Sprite Y Size

Use this register to control the size of the mosaic on backgrounds/sprites that have mosaic enabled..

0x04000050 - REG_BLDCNT

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X T S  R Q P O  M M L K  J I H G 
BitsDescription
0 (G)Blend BG0 (source)
1 (H)Blend Bg1 (source)
2 (I)Blend BG2 (source)
3 (J)Blend BG3 (source)
4 (K)Blend sprites (source)
5 (L)Blend backdrop (source)
6-7 (M)

Blend Mode

There are four different modes:

00 = All effects off
01 = Alpha blend
10 = Lighten (fade to white)
11 = Darken (fade to black)

8 (O)Blend BG0 (target)
9 (P)Blend BG1 (target)
A (Q)Blend BG2 (target)
B (R)Blend BG3 (target)
C (S)Blend sprites (target)
D (T)Blend backdrop (target)

Use this register to determine the blending mode and which layer(s) you wish to perform blending on. In the case of alpha blends (Mode 01), specify the layers that are "on top" using the source flags (bits 0 - 5) and the layers that are on the bottom using the target flags (bits 8-13). The target layer must be below the source layer in terms of its priority, or the blend will not take effect.

Other things to note about alpha blends:

  • If there is more than one target layer, the blend will only occur for a target with lower priority in areas where it shows through targets of higher priority due to the transparent pixel being set
  • Source layers will only blend with areas of a target layer that are visible beneath them. If another layer is blocking the way (even if it is another source layer), there will be no blend and the original source color will be drawn.
  • As a result of these two conditions, it is never possible for any given pixel to be a blend of more than 2 layers. This eliminates the possiblity of using these registers to have 3 or more layers of translucent graphics showing through one another.
  • A layer cannot blend with itself.
  • If an obj has semi-transparency enabled, it will blend normally (as if it were specified as a source layer)
  • Unfortunately, it is not possible to alpha blend sprites against one another, no matter how your prioritize them. Alpha blended sprites that are "in front of" other sprites will blend with the other target layers while still occluding the sprites behind them (i.e. it will look like the portion of the non-blended sprite that is behind the blended one has disappeared), for a most unnatural effect.

0x04000052 - REG_BLDALPHA (Write Only)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X X B  B B B B  X X X A  A A A A 
BitsDescription
0-4 (A)Coefficient A, the source pixel (layer above)
8-C (B)Coefficient B, the target pixel (layer below)

Use this in conjunction with REG_BLDCNT to determine the amount of blending between layers. An unblended pixel of normal intensity is is considered to have a coefficient of 16. Coefficient A and Coefficient B determine the ratio of each of the sources that will get mixed into the final image. Thus, if A is 12 and B is 4, the resulting image will appear to be 12/16 the color of A and 4/16 the color of B. Note that A and B can add up to be greater than 16 (for an additive or brightening effect) or less than 16 (for a darkening effect).

0x04000054 - REG_BLDY (Write Only)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X X X  X X X X  X X X F  F F F F 
BitsDescription
0-4 (F)The lighten/darken value

This is the amount by which to lighten or darken the source layers (as specified in REG_BLDCNT) . The higher the value, the greater the fade. 16 is the peak fade value; values from 16 - 31 shade the layer with either pure black (for a darken) or pure white (for a lighten).


0x040000060 - 0x0400000A6 (Sound Controls)

Note: I've obtained this info (most of it verbatim) from Uze's BeLogic unofficial GBA sound info site, which gives a much more thorough explanation as well as some sample source code and demos. Thanks to Uze for providing such a great resource on GBA sound.

0x04000060 - REG_SOUND1CNT_L (Sound 1 Sweep control)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X X X  X X X X  X T T T  A S S S
BitsDescription
0-2 (S)

Number of sweep shifts. These control the amount of change in frequency (either increase or decrease) at each change. The wave's new period is given by: T=T±T/(2n), where n is the sweep shift's value.

3 (A)

Sweep increase or decrease. When decrementing, if the frequency value gets smaller than zero, the previous value is retained. When incrementing, if the frequency gets greater than the maximum frequency (131Khz or 2048 for the register value) the sound stops.

0 = Addition (frequency increase)
1 = Subtraction (frequency decrease)

4-6 (T)

Sweep Time. This is the delay between sweep shifts. After each delay, the frequency increments or decrements.

000: Disable sweep function
001: Ts=1 / 128khz (7.8 ms)
010: Ts=2 / 128khz (15.6 ms)
011: Ts=3 / 128 khz (23.4 ms)
100: Ts=4 / 128 khz (31.3 ms)
101: Ts=5 / 128 khz (39.1 ms)
110: Ts=6 / 128 khz (46.9 ms)
111: Ts=7 / 128 khz (54.7 ms)

Sound channel 1 produces a square wave with envelope and frequency sweep functions. This register controls the frequency sweep function. When the sweep function is not required, set the sweep time to zero and set the increase/decrease bit to 1.

0x04000062 - REG_SOUND1CNT_H (Sound 1 Length, wave duty and envelope control)

                      W W  W W W W
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
I I I I  M T T T  D D L L  L L L L
BitsDescription
0-5 (L)

Sound length. This is a 6 bit value obtained from the following formula:

Sound length = (64-register value)*(1/256) seconds

After the sound length has been changed, the sound channel must be resetted via bit F of REG_SOUND1CNT_X (when using timed mode).

6-7 (D)

Wave duty cycle. This controls the percentage of the ON state of the square wave.

00 = 12.5%
01 = 25%
10 = 50%
11 = 75%

8-A (T)

Envelope step time. This is the delay between successive envelope increase or decrease. It is given by the following formula:

Time = register value * (1/64) seconds

B (M)

Envelope mode. Controls if the envelope is to increase or decrease in volume over time.

0 = Envelope decreases
1 = Envelope increases

C-F (I)

Initial Envelope value. 1111 produces the maximum volume and 0000 mutes the sound. When sound 1 is playing, modifying the volume envelope bits has no effect until the sound is resetted.

0x04000064 - REG_SOUND1CNT_X (Sound 1 Frequency, reset and loop control)

W          W W W  W W W W  W W W W
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
R T X X  X F F F  F F F F  F F F F
BitsDescription
0-A (F)

Sound frequency. The minimum frequency is 64Hz and the maximum is 131Khz. Can be calculated from the following formula:

F(hz) = 4194304 / (32 * (2048-register value))

E (T)

Timed sound. When set to 0, sound 1 is played continuously regardless of the length data in REG_SOUND1CNT_H. When set to 1, sound is played for that specified length and after that, bit 0 of REG_SOUNDCNT_X is reset.

F (R)

Sound reset. When set, sound resets and restarts at the specified frequency. When sound 1 is playing, modifying the volume envelope bits has no effect until the sound is resetted. Frequency and sound reset must be perfomed in a single write since both are write only. Frequency can always be changed without resetting the sound channel.

0x04000068 - REG_SOUND2CNT_L (Sound 2 Length, wave duty and envelope control)

                      W W  W W W W
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
I I I I  M T T T  D D L L  L L L L
BitsDescription
0-5 (L)

Sound length. This is a 6 bit value obtained from the following formula:

Sound length = (64-register value)*(1/256) seconds.

After the sound length has been changed, the sound channel must be resetted via bit F of REG_SOUND1CNT_X (when using timed mode).

6-7 (D)

Wave duty cycle. This controls the percentage of the ON state of the square wave.

00 = 12.5%
01 = 25%
10 = 50%
11 = 75%

8-A (T)

Envelope step time. This is the delay between successive envelope increase or decrease. It is given by the following formula:

Time = register value * (1/64) seconds.

B (M)

Envelope mode. Controls if the envelope is to increase or decrease in volume over time.

0 = Envelope decreases
1 = Envelope increases

C-F (I)

Initial Envelope value. 1111 produces the maximum volume and 0000 mutes the sound. When sound 2 is playing, modifying the volume envelope bits has no effect until the sound is resetted.

0x0400006C- REG_SOUND2CNT_H (Sound 2 Frequency, reset and loop control)

W          W W W  W W W W  W W W W
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
R T X X  X F F F  F F F F  F F F F
BitsDescription
0-A (F)

Sound frequency. The minimum frequency is 64Hz and the maximum is 131Khz. Can be calculated from the following formula:

F(hz) = 4194304 / (32 * (2048-register value))

E (T)

Timed sound. When set to 0, sound 2 is played continuously regardless of the length data in REG_SOUND2CNT_L. When set to 1, sound is played for that specified length and after that, bit 1 of REG_SOUNDCNT_X is reset.

F (R)

Sound reset. When set, sound resets and restarts at the specified frequency. When sound 2 is playing, modifying the volume envelope bits has no effect until the sound is resetted. Frequency and sound reset must be perfomed in a single write since both are write only. Frequency can always be changed without resetting the sound channel.

0x04000070 - REG_SOUND3CNT_L (Sound 3 Enable and wave ram bank control)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X X X  X X X X  N S M X  X X X X
BitsDescription
5 (M)Bank Mode (0 = 2 x 32 sample banks, 1 = 1 x 64 sample bank)
6 (S)Bank Select. Controls which bank is active for playing/reloading. If set to 0, samples are played from bank 0 and writing to the Wave Ram will store the data in Bank 1, and vice-versa.
7 (N)Sound Channel 3 output enable. When this is set and bit 15 from REG_SOUND3CNT_X is set, the sound starts to play.

Sound channel 3 is a circuit that can produce an arbitrary wave pattern. Samples are 4 bit, 8 samples per word, and are located in Wave Ram registers from 0x400090 to 0x40009F. The Wave Ram is banked, providing the ability to play a 64 samples pattern or to select between two 32 samples patterns (Bit 5). Sound channel 3 always produces some audio artifacts (distortion) when sound is initialized. Fortunately, switching banks does not require re-initialisation during playback, thus allowing for dynamic reloading of the Wave Ram without generating any distortion.

Both banks of Wave Ram are filled with zero upon initialization of the Gameboy, Bank 0 being selected. So writing to bank 0 implies setting bit 6 to 1 before loading Wave Ram then set it back to 0 to play it.

0x04000072 - REG_SOUND3CNT_H (Sound 3 Sound length and output level control)

                  W W W W  W W W W
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
R R R X  X X X X  L L L L  L L L L
BitsDescription
0-7 (L)

Sound length. The sound length is an 8 bit value obtained from the following formula:

Register = Note length (in seconds) * 256

Hence a 1 second maximum and a 3.9 millisecond minimum sound duration. After the sound length has be changed, the sound channel must be resetted via bit F of REG_SOUND3CNT_X.

D-F (R)

Output volume ratio:

000 = Mute
001 = 100%
100 = 75%
010 = 50%
011 = 25%

0x04000074 - REG_SOUND3CNT_X (Sound 3 Frequency, reset and loop control)

W          W W W  W W W W  W W W W
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
R T X X  X F F F  F F F F  F F F F
BitsDescription
0-A (F)

Sound frequency. The minimum frequency is 64Hz and the maximum is 131Khz. Can be calculated from the following formula:

F(hz) = 4194304 / (32 * (2048-register value))

E (T)

Timed sound. When set to 0, sound 3 is played continuously regardless of the length data in REG_SOUND3CNT_H. When set to 1, sound is played for that specified length and after that, bit 2 of REG_SOUNDCNT_X is reset.

F (R)

Sound reset. When set, sound resets and restarts at the specified frequency. Frequency and sound reset must be perfomed in a single write since both are write only. In continuous mode, frequency can be changed without resetting the sound channel.

0x04000078 - REG_SOUND4CNT_L (Sound 4 Length, output level and envelope control)

                     W W  W W W W
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
I I I I  M T T T  X X L L  L L L L
BitsDescription
0-5 (L)

Sound length. This is a 6 bit value obtained from the following formula:

Sound length = (64-register value)\*(1/256) seconds

After the sound length has been changed, the sound channel must be resetted via bit F of REG_SOUND4CNT_H (when using timed mode).

8-A (T)

Envelope step time. This is the delay between successive envelope increase or decrease. It is given by the following formula:

Time = register value * (1/64) seconds

B (M)

Envelope mode. Controls if the envelope is to increase or decrease in volume over time.

0 = Envelope decreases
1 = Envelope increases

D-F (I)

Initial Envelope value. 1111 produces the maximum volume and 0000 mutes the sound.

0x0400007C - REG_SOUND4CNT_H (Sound 4 Noise parameters, reset and loop control)

W
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
R T X X  X X X X  P P P P  S C C C
BitsDescription
0-2 (C)

Clock divider frequency. This divides the CPU frequency. Its output is then fed into the counter's pre-scaler (controlled by bits 4-7) which further devides the frequency.

000 = f*2 (f = 4.194304 Mhz/8)
001 = f
010 = f/2
011 = f/3
100 = f/4
101 = f/5
110 = f/6
111 = f/7

3 (S)

Counter stages: 0 = 15 stages, 1 = 7 stages. This controls the period of the polynomial counter. It is given by (2^n)-1 where n is the number of stages. So for n=7, the pseudo-noise period lasts 63 input clocks. After that, the counter restarts the same count sequence.

4-7 (P)

Counter Pre-Stepper frequency:

0000 = Q/2
0001 = Q/2^2
0010 = Q/2^3
0011 = Q/2^4
....
1101 = Q/2^14
1110 = Not used
1111 = Not used

Where Q is the clock divider's output frequency.

E (T)

Timed sound. When set to 0, sound 4 is played continuously regardless of the length data in REG_SOUND4CNT_L. When set to 1, sound is played for that specified length and after that, bit 3 of REG_SOUNDCNT_X is reset.

F (R)

Sound reset. When bit F is set to 1, Envelope is set to initial value, the LFSR count sequence is resetted and the sound restarts. In continuous mode, all parameters can be changed but the sound needs to be resetted when modifying the envelope initial volume or the clock divider for changes to take effects.

Channel 4 produces pseudo-noise generated by a polynomial counter. It is based on a 7/15 stages linear-feedback shift register (LFSR). LFSR counts in a pseudo-random order where each state is generated once and only once during the whole count sequence. The sound is produced by the least significant bit's output stage.

0x04000080 - REG_SOUNDCNT_L (Sound 1-4 Output level and Stereo control)

                           ?
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
R Q P O  N M L K  J I I I  H G G G
BitsDescription
0-2 (G)DMG Left Volume
3 (H)Vin Left on/off (?) - According to BeLogic, Vin on/off allowed the original GameBoy paks to provide their own sound source. It is unkown whether they still work on a GBA.
4-6 (I)DMG Right Volume
7 (J)Vin Right on/off (?)
8 (K)DMG Sound 1 to left output
9 (L)DMG Sound 2 to left output
A (M)DMG Sound 3 to left output
B (N)DMG Sound 4 to left output
C (O)DMG Sound 1 to right output
D (P)DMG Sound 2 to right output
E (Q)DMG Sound 3 to right output
F (R)DMG Sound 4 to right output

This register controls only the DMG output amplifiers and have no effects on the individual sound channels' processing, or Direct Sound channels' volume.

0x04000082 - REG_SOUNDCNT_H (Direct Sound control and Sound 1-4 output ratio)

W        W      
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
Q P O N  M L K J  X X X X  I H G G
BitsDescription
0-1 (G)

Output Sound Ratio for channels 1-4.

00 = 25%
01 = 50%
10 = 100%
11 = ??

2 (H)Direct sound A output ratio (0 - 50%, 1 - 100%)
3 (I)Direct sound B output ratio (0 - 50%, 1 - 100%)
8 (J)Direct Sound A to right output
9 (K)Direct sound A to left output
A (L)Direct sound A Sampling rate timer (timer 0 or 1). Use this to set which timer contorls the playback frequency.
B (M)Direct sound A FIFO reset
C (N)Direct sound B to right output
D (O)Direct sound B to left output
E (P)Direct sound B Sampling rate timer (timer 0 or 1). Use this to set which timer controls the playback frequency.
F (Q)Direct sound B FIFO reset

This register is used in controlling Direct Sound on the GBA. Output ratios control the volume, in percentage, that gets output to the speakers.

0x04000084 - REG_SOUNDCNT_X (Master sound enable and Sound 1-4 play status)

                           R R R R
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X X X  X X X X  N X X X  J I H G
BitsDescription
0 (G)DMG Sound 1 Status (Read only). 0 = Stopped, 1 = Playing
1 (H)DMG Sound 2 Status (Read only). 0 = Stopped, 1 = Playing
2 (I)DMG Sound 3 Status (Read only). 0 = Stopped, 1 = Playing
3 (J)DMG Sound 4 Status (Read only). 0 = Stopped, 1 = Playing
7 (N)All Sound circuit enable

This register is used to monitor the play status of sounds and to turn on or off all sound circuits. Turning the sound circuits off saves battery power, allowing them to last up to 10% longer.

0x04000088 - REG_SOUNDBIAS (Sound bias and Amplitude resolution control)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
R R X X  X X B B  B B B B  B B B X
BitsDescription
1-9 (B)PWM bias value, controlled by the BIOS.
E-F (R)Amplitude resolutions
00 = 9 bit at 32768 hz
01 = 8 bit at 65536 hz
10 = 7 bit at 131072 hz
11 = 6 bit at 262144 hz

The BIAS setting is used to offset the sound output and bring it back into a signed range. When the BIOS starts up, it runs a timing loop where it slowly raises the BIAS voltage from 0 to 512. This setting should not be changed. At best, the sound will become distorted. At worst the amplifier inside the GBA could be damaged.

When accessing bits F-E, a read-modify-write is required. The default value for bits F-E is 00. Most if not all games use 01 for this setting.

0x04000090 - REG_WAVE_RAM0_L (Sound 3 samples 0-3)
0x04000092 - REG_WAVE_RAM0_H (Sound 3 samples 4-7)
0x04000094 - REG_WAVE_RAM1_L (Sound 3 samples 8-11)
0x04000096 - REG_WAVE_RAM1_H (Sound 3 samples 12-15)
0x04000098 - REG_WAVE_RAM2_L (Sound 3 samples 16-19)
0x0400009A - REG_WAVE_RAM2_H (Sound 3 samples 20-23)
0x0400009C - REG_WAVE_RAM3_L (Sound 3 samples 23-27)
0x0400009E - REG_WAVE_RAM3_H (Sound 3 samples 28-31)

These registers together contain four (4 bytes each) 4-bit wave RAM samples for Sound channel 3.

0x040000A0 - REG_FIFO_A_L (Direct Sound channel A samples 0-1)(Write Only)
0x040000A2 - REG_FIFO_A_H (Direct Sound channel A samples 2-3)(Write Only)
0x040000A4 - REG_FIFO_B_L (Direct Sound channel B samples 0-1)(Write Only)
0x040000A6 - REG_FIFO_B_H (Direct Sound channel B samples 2-3)(Write Only)

These are the locations of the Direct Sound 8-bit FIFO samples, from which Direct Sound pulls the music data to be played on the speakers. Note that there are only 8 bytes total for all your samples. You repeatedly fill these from a buffer of your own using DMA0 or DMA1, or by using timer [interrupts](#Hardware Interrupts).

To fill them using DMA, first set Timer 0 or Timer 1 to refresh at the appropriate sample rate (for example, 16khz). Next, set the DMA source address to a sound sample in memory, and the destination address to one of these FIFO registers. Use REG_SOUNTCNT_H to reset FIFO and tell Direct Sound to get its sampling rate from Timer 0 or Timer 1. Finally, set the DMA control register to start on FIFO empty (start mode 11) and to repeat, then enable the timers. All of this will cause the hardware to play sound samples in FIFO at the rate specified in your timer, and automatically refill them using DMA.

To fill these using interrupts, follow a similar process, but instead of using DMA, set the clock to interrupt on overflow. When using interrupts instead of DMA, BeLogic recommends setting the timer divider to 1024 and start the timer at 0xFFFF order to get a sampling rate of 16.384 khz. This apparently causes less distortion than if you simply set the start time of the clock to 0xFFFF - (2^24/16000).

Note that reading from these registers can yield unpredictable results. It might be interesting to see just how unpredictable...


0x040000B0, 0x040000BC, 0x040000C8, 0x040000D4 (DMA Source Registers)(Write Only)

0x040000B0 - REG_DMA0SAD (DMA0 Source Address) (Write Only)

31 30 29 28  27 26 25 24  23 22 21 20  19 18 17 16  15 14 13 12  11 10 9 8  7 6 5 4  3 2 1 0
X  X  X  X   X  A  A  A   A  A  A  A   A  A  A  A   A  A  A  A   A  A  A A  A A A A  A A A A
BitsDescription
0-26 (A)27-bit source address

This is the source address for DMA channel 0 transfers. Note that it is 27-bit.

0x040000BC - REG_DMA1SAD (DMA1 Source Address)
0x040000C8 - REG_DMA2SAD (DMA2 Source Address)
0x040000D4 - REG_DMA3SAD (DMA3 Source Address)

31 30 29 28  27 26 25 24  23 22 21 20  19 18 17 16  15 14 13 12  11 10 9 8  7 6 5 4  3 2 1 0
X  X  X  X   A  A  A  A   A  A  A  A   A  A  A  A   A  A  A  A   A  A  A A  A A A A  A A A A
BitsDescription
0-27 (A)28-bit source address

This is the source address for DMA channel 1, 2, or 3 transfers. Note that it is 28-bit.

0x040000B4, 0x040000C0, 0x040000CC, 0x040000D8 (DMA Destination Registers) (Write Only)

0x040000B4 - REG_DMA0DAD (DMA0 Destination Address)
0x040000C0 - REG_DMA1DAD (DMA1 Destination Address)
0x040000CC - REG_DMA2DAD (DMA2 Destination Address)

31 30 29 28  27 26 25 24  23 22 21 20  19 18 17 16  15 14 13 12  11 10 9 8  7 6 5 4  3 2 1 0
X  X  X  X   X  A  A  A   A  A  A  A   A  A  A  A   A  A  A  A   A  A  A A  A A A A  A A A A
BitsDescription
0-27 (A)27-bit destination address

This is the dest address for DMA channel 0, 1, and 2 transfers. Note that it is 27-bit.

0x040000D8 - REG_DMA3DAD (DMA3 Destination Address)(Write Only)

31 30 29 28  27 26 25 24  23 22 21 20  19 18 17 16  15 14 13 12  11 10 9 8  7 6 5 4  3 2 1 0
X  X  X  X   A  A  A  A   A  A  A  A   A  A  A  A   A  A  A  A   A  A  A A  A A A A  A A A A
BitsDescription
0-27 (A)28-bit destination address

This is the dest address for DMA channel 3 transfers. Note that it is 28-bit.

0x040000B8, 0x040000C4, 0x040000D0, 0x040000DC (DMA Count Registers) (Write Only)

0x040000B8 - REG_DMA0CNT_L (DMA0 Count Register)
0x040000C4 - REG_DMA1CNT_L (DMA1 Count Register)
0x040000D0 - REG_DMA2CNT_L (DMA2 Count Register)
0x040000DC - REG_DMA3CNT_L (DMA3 Count Register)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X L L  L L L L  L L L L  L L L L 
BitsDescription
0-D (L)Number of words or halfwords to copy

0x040000BA, 0x040000C6, 0x040000D2, 0x040000DE (DMA Control Registers)

(Note: In some places you will see the DMA control and DMA count registers depicted as a single 32-bit register called REG_DMAXCNT. I opted to treat them as two 16-bit registers for sake of clarity.)

0x040000BA - REG_DMA0CNT_H (DMA0 Control Register)
0x040000C6 - REG_DMA1CNT_H (DMA1 Control Register)
0x040000D2 - REG_DMA2CNT_H (DMA2 Control Register)
0x040000DE - REG_DMA3CNT_H (DMA3 Control Register)

         ?             
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
N I M M  U S R A  A B B X  X X X X
BitsDescription
5-6 (B)

Type of increment applied to destination address. If enabled, the address will be incremented/decremented by 2 or 4 bytes, depending on the selected size. When the DMA is activated, the contents of these registers are copied to internal counters in the DMA hardware, which then increments/decrements these registers during transfer, preserving the contents of the IORAM registers.*

00 = Increment after each copy
01 = Decrement after each copy
10 = Leave unchanged
11 = Increment without after each copy, reset to initial value at the end of transfer (or at the end of the current repetition)

7-8 (A)

Type of increment applied to source address:

00 = Increment after each copy
01 = Decrement after each copy
10 = Leave unchanged
11 = Illegal

Note: I am somewhat uncertain about option "11" for both of these. Can anyone confirm?

9 (R)Repeat. When in start modes 1 or 2, this bit causes the transfer to repeat for each interval.
A (S)Size. If set, copy 32-bit quantities (words) If clear, copy 16-bit quantities (half words)
B (U)Unknown. For DMA 0, 1, and 2, this bit is read only and set to 0. However, for DMA 3, it appears to be writeable. Thoughts, anyone?
C-D (M)

Start Mode.

00 = Transfer immediately
01 = Transfer on vblank (i.e. vdma)
10 = Transfer on hblank (i.e. hdma. Note that, unlike h-interrupts, hdma does NOT occur during vblank.)
11 = The function of this varies based on the DMA channel.

For DMA 1 or 2: Instructs the DMA to repeat on FIFO-empty requests. When this is set the size and count are ignored and a single 32 bit quantity is transferred on FIFO empty.

For DMA 3: Apparently allows transfers to start at the beginning of a rendering line, copying data into a buffer as the line is being drawn on the screen. Useful for flicker-free transfers in mode 3, which has no backbuffer.

E (I)IRQ. Setting this bit causes the DMA to generate an interrupt when it is done with the data transfer.
F (N)Set this bit to enable DMA operation. Clear to end DMA operation.

This address controls a DMA transfer which allows large amounts of data to be transferred from one area of memory to another. It is theoretically twice as fast as transfering by the CPU, which uses at least one cycle for a read instruction and another for a write. DMA can also be used to clear memory to a constant value, if the source address is not incremented with each copy. Fist, set the DMASAD and DMADAD registers to point to the addresses you want. Writing to DMACNT_H address with a '1' in the N field and a '00' in the M field will start the transfer immediately.

DMA transfers may occur on an interrupt if the start mode bits are set for this. DMAs have a priority ranking with 3 at the lowest and 0 at the highest. For most cases, program code will be using DMA3 as it is lowest priority, allowing it to be interrupted by more important DMA (see below).

Specific DMAs have the following properties:

  • DMA0: This DMA is the highester priority, but cannot be used to access cartridge memory (addresses 0x08000000 and higher). It is suitable for time-critical operations such as transfering scale and rotate data to the background scaling registers. Since it takes precedence over other DMAs, it will not be postponed or interrupted (possibly causing undesirable results such as screen artifacts).

  • DMA1 and DMA2: These are the only DMA that can be used for sound FIFO. If start mode "11" is set, the DMA will be triggered on FIFO empty. I believe that FIFO A always sends its empty requests to DMA1 and that FIFO B sends its empty requests only to DMA2, though I don't have any verification of this.

  • DMA3: This is is the lowest priority and thus often used as a "general purpose" DMA. Using this DMA for your basic memory transfers ensures that sound FIFO DMA and other time-critical DMA are not delayed, making audio or visual artifacts less likely.

* (Originally I had assumed a direct mapping between the source/destination registers and the current transfer address, and thus this section of the doc distinguished between transfers which wrote-back to the registers and those which did not. This appears to have been an incorrect assumption, and was brought to light as I delved further into sound emulation)

DMA Transfer Ratings

The following table lists the cycle timings for various DMA transfers. The format of each entry is:

16 bit DMA / 32 bit DMA

Units are in cycles per item transfered. Thus, a rating of 4/8 indicates that the transfer takes 4 cycles for every 16 bits transferred with 16 bit DMA, or 8 cycles for every 32 bits transfered with 32 bit DMA.

Source       Destination
             EWRAM    IWRAM    IO       PAL RAM  VRAM     OAM
ROM 0 WS     4/8      2/3      2/3      2/4      2/4      2/3
ROM 1 WS     5/10     3/5      3/5      3/6      3/6      3/5
ROM 2 WS     6/12     4/7      4/7      4/8      4/8      4/7
EWRAM        6/12     4/7      4/7      4/8      4/8      4/7
IWRAM        4/7      2/2      2/2      2/3      2/3      2/2
I/O          4/7      2/2      2/2      2/3      2/3      2/2
PAL RAM      4/8      2/2      2/3      2/4      2/4      2/2
VRAM         4/8      2/3      2/3      2/4      2/4      2/2
OAM          4/7      2/2      2/2      2/3      2/3      2/2

Note that it is not possible to DMA transfer from or to SRAM (Cart RAM) or BIOS, and (obviously) it is not possible to transfer to ROM.

Thanks to Kay for supplying these transfer statistics!!




0x04000100 - 0x0400010E (Timer registers)

0x04000100 - REG_TM0D (Timer 0 Data)
0x04000104 - REG_TM1D (Timer 1 Data)
0x04000108 - REG_TM2D (Timer 2 Data)
0x0400010C - REG_TM3D (Timer 3 Data)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
D D D D  D D D D  D D D D  D D D D
BitsDescription
0-F (D)Current count of the timer.

Note that these registers are R/W. The default is to start counting from 0x0000, but if a value is written to this register, the timer will henceforth use that as a starting value. Thus the rate at which timers overflow and generate interrupts (see REG_TMXCNT, below) can be customized.

Timer 0 and Timer 1 are used to control the rate of Direct Sound FIFO. When using DMA with start mode 11, they can automatically cause it to refill the FIFO.

To set the rate of playback in hz, write the value 0xFFFF - (2^24/Plaback Freq in hz) to the register. This sets the start value such that the timer will overflow precisely when the next sound sample is needed, and cause the DMA to activate.

When using interrupts, set the start value of these to 0, but use REG_TMXCNT to change the update frequency to 1024, thus causing an interrupt rate of 16.384khz.

0x04000102 - REG_TM0CNT (Timer 0 Control)
0x04000106 - REG_TM1CNT (Timer 1 Control)
0x0400010A - REG_TM2CNT (Timer 2 Control)
0x0400010E - REG_TM3CNT (Timer 3 Control)

                             *
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X X X  X X X X  E I X X  X C F F
BitsDescription
0-1 (F)

Frequency at which the timer updates.

00 = Default frequency (full) - 16.78MHz (~17mlns ticks per second)
01 = Every 64 clock pulses - ~262187.5KHz
10 = Every 256 clock pulses - ~65546.875KHz
11 = Every 1024 clock pulses - ~16386.71875KHz

2 (C)

Cascade (* Unused on TM0) - When this bit is set, the frequency of this timer is ignored. Instead the timer increments when the timer below it overflows. For example, if timer 1 is set to cascade, it will increment whenever timer 0's value goes from 0xFFFF to 0x0000.

6 (I)Generate an interrupt on overflow
7 (E)Enable the timer.


0x04000120 - 0x0400012A - Serial Communication Registers

Note: All of the serial comm information originates from Andrew May's description of the GBA linker hardware, which in turn was compiled from various other sources on the web. My thanks to ePAc for discovering his site and putting the information into a format consistent with the rest of this spec. If anybody else has information to add to this, please send us a PR.

0x04000120 - REG_SCD0 (Master/Slave 0 destination reg) (Read Only)
0x04000122 - REG_SCD1 (Slave 1 destination reg) (Read Only)
0x04000124 - REG_SCD2 (Slave 2 destination reg) (Read Only)
0x04000126 - REG_SCD3 (Slave 3 destination reg) (Read Only)


R R R R  R R R R  R R R R  R R R R
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
D D D D  D D D D  D D D D  D D D D
BitsDescription
0-F (D)The data received.
  • SCD0 contains the data sent by the master (also called slave 0)
  • SCD1 contains the data sent by the first slave (slave1)
  • SCD2 contains the data sent by the second slave (slave2)
  • SCD3 contains the data sent by the last slave (slave3)

0x04000128 - REG_SCCNT_L (Serial Communication channel control register)

                    R                
F E D C  B A 9 8  7 6 5 4  3 2 1 0
X I M M  X X X X  S E D D  L L B B
BitsDescription
0-1 (B)Baud rate - 00 = 9600, 01 = 38400,10 = 57600, 11 = 115200
2-3 (L)SD (bit3) and SI (bit2) line direct access
4-5 (D)ID of GBA - 00 = master, 01 = slave1, 10 = slave2, 11 = slave3
6 (E)Error (1 on error)
7 (S)Start Transfer (1 triggers the start on the MASTER ONLY)
C-D (M)Comm Mode - 00 = 8bit, 01 = 32bit, 10 = Multilink, 11 = UART
E (I)Enable Comm Interupt

Using the link port and a link cable, the GBA can transmit serial data in one of four modes: 8 bit, 32 bit, Multilink, and UART. At the moment this document only contains info on the multilink mode. Please send us a PR if you know more about the other modes.

To transfer data in this mode, you must coordinate the actions of all the GBAs which are linked together. Each GBA slave must place the data they wish transfered in REG_SCCNT_H. Then the Master/Slave 0 initiates the transfer by setting bit 7 of REG_SCCNT_L. This causes the hardware to transfer the data and, as I understand, it will magically appear in the destination registers of each slave, according to the following:

Thus each GBA in the chain has a duplicate of the data.

It is unclear to me how each GBA knows what ID it is; perhaps this value is automatically set when the link cable is attached? ePAc has commented that the master is the GBA in the set that has the purple connector connected to its ext port. So if you have a GBA that want to be a MBserver for a set of clients, then you need to put the cart in the one with the purple connector.

Note from me: I have a suspicion that some of these bits are write-only. Please let me know if you find out more.

0x0400012A - REG_SCCNT_H (Serial Communication Source Register)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
S S S S  S S S S  S S S S  S S S S
BitsDescription
0-F (S)The data to be sent over the link cable.

Addresses 0x04000130 - 0x04000132 - Keypad Input and Control Registers

0x04000130 - REG_KEYINPUT (The input register) (Read Only)

             R R  R R R R  R R R R
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X X X  X X J I  D U L R  S E B A 
BitsDescription
0 (A)A button
1 (B)B button
2 (E)Select button
3 (S)Start button
4 (R)D-pad Right
5 (L)D-pad Left
6 (U)D-pad Up
7 (D)D-pad Down
8 (I)Right shoulder button
9 (J)Left shoulder button

This register stores the state of the GBA's buttons. Each of the inputs is active low. This means that a '0' bit indicates that the key is pressed, while a '1' bit indicates that the key is not pressed. In general a game which samples these (rather than using interrupts) should do so at least once every refresh (60hz), or more in the case of fast action fighting games (like Street Fighter).

0x04000132 - REG_KEYCNT (Key Control Register)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
T K X X  X X J I  D U L R  S E B A
BitsDescription
0 (A)A button
1 (B)B button
2 (E)Select button
3 (S)Start button
4 (R)D-pad Right
5 (L)D-pad Left
6 (U)D-pad Up
7 (D)D-pad Down
8 (I)Right shoulder button
9 (J)Left shoulder button
E (K)Generate interrupt on keypress
F (T)

Interrupt "type"

0 = "OR" operation: interrupt will be generated if any of specified keys (bits 0-9) are pressed
1 = "AND" operation: interrupt will be generated if all specified keys are pressed at the same time.

Use this register to set which keypresses generate interrupts. The appropriate bits must also be set in REG_IE and REG_IME.


0x04000134 - REG_RCNT

    R R  R R R                 R R  
F E D C  B A 9 8  7 6 5 4  3 2 1 0

This register appears to give direct access to the different lines of the link port. If you happen to have more information about which bit corresponds to which line, please send us a PR or get in touch on IRC or Discord.

0x04000200 - 0x04000208 - Interrupt Registers

0x04000200 - REG_IE (Interrupt Enable Register)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X T Y  G F E D  S L K J  I C H V
BitsDescription
0 (V)VBlank Interrupt
1 (H)HBlank Interrupt
2 (C)VCount Interrupt
3 (I)Timer 0 Interrupt
4 (J)Timer 1 Interrupt
5 (K)Timer 2 Interrupt
6 (L)Timer 3 Interrupt
7 (S)Serial Communication Interrupt
8 (D)DMA0 Interrupt
9 (E)DMA1 Interrupt
A (F)DMA2 Interrupt
B (G)DMA3 Interrupt
C (Y)Key Interrupt
D (T)Cartridge Interrupt

Use this register to mask out which interrupts are enabled or disabled.

0x04000202 - REG_IF (Interrupt Flags Regster)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X T Y  G F E D  S L K J  I C H V
BitsDescription
0 (V)VBlank Interrupt
1 (H)HBlank Interrupt
2 (C)VCount Interrupt
3 (I)Timer 0 Interrupt
4 (J)Timer 1 Interrupt
5 (K)Timer 2 Interrupt
6 (L)Timer 3 Interrupt
7 (S)Serial Communication Interrupt
8 (D)DMA0 Interrupt
9 (E)DMA1 Interrupt
A (F)DMA2 Interrupt
B (G)DMA3 Interrupt
C (Y)Key Interrupt
D (T)Cartridge Interrupt

This register will determine which interrupt is currently being serviced. When your interrupt service routine get scalled, check these flags to determine what called it. In order to keep yourself from servicing the wrong interrupt at a later time, you should reset the flags to 0 by writing a 1 to them.

0x04000204 - REG_WAITCNT (Wait State Control)

R   
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
G P X C  C N M M  L K K J  I I S S
BitsDescription
0-1 (S)

SRAM wait state

00 = 4 cycles, 01 = 3 cycles
10 = 2 cycles, 11 = 8 cycles

2-3 (I)

Bank 0x08000000 initial wait state

00 = 4 cycles, 01 = 3 cycles
10 = 2 cycles, 11 = 8 cycles

4 (J)

Bank 0x08000000 subsequent wait state

0 = 2 cycles, 1 = 1 cycle

5-6 (K)

Bank 0x0A000000 initial wait state

00 = 4 cycles, 01 = 3 cycles
10 = 2 cycles, 11 = 8 cycles

7 (L)

Bank 0x0A000000 subsequent wait state

0 = 4 cycles, 1 = 1 cycle

8-9 (M)

Bank 0x0C000000 initial wait state

00 = 4 cycles, 01 = 3 cycles
10 = 2 cycles, 11 = 8 cycles

A (N)

Bank 0x0C000000 subsequent wait state

0 = 8 cycles, 1 = 1 cycle

B-C (C)

Cart clock. Don't touch.

00 = Terminal output clock fixed lo
01 = 4 Mhz
10 = 8 Mhz
11 = 16 Mhz

E (P)

Prefetch. The GBA's 8-word-by-16-bit prefetch buffer makes subsequent ROM reads faster in code that accesses both ROM and RAM.

0 = Disable (and save battery power)
1 = Enable

F (G)

Game Pak type

0 = AGB multiplexed bus
1 = DMG/CGB bus)

Use this register to control wait state settings and the prefetch buffer for ROM and SRAM. Thanks to Damian Yerrick for contributing this info, and for pointing me to some relevant reading material.

0x04000208 - REG_IME (Interrupt Master Enable)

F E D C  B A 9 8  7 6 5 4  3 2 1 0 
X X X X  X X X X  X X X X  X X X M 
BitsDescription
0 (M)Master interrupt enable. When off, all interrupts are disabled. This must be on for the interrupt bits in REG_IE to have any effect.



0x04000300 - REG_HALTCNT

? ? ? ?  ? ? ? ?  ? ? ? ?  ? ? ? ?
F E D C  B A 9 8  7 6 5 4  3 2 1 0 
P M X X  X X X X  X X X X  X X X X
BitsDescription
F (M)Mode
E (P)Power down

I've written down the function of this as it appears in Mappy's SDK. However, I can't say how it works. Writing values to bits 14 and 15 seems to have no effect. This register shows up as 0x0001 when read. As always, send me mail if you have more info on this.